
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:03:18 04/23/2012
-- Design Name:   regFile
-- Module Name:   C:/Xilinx92i/regFile/testbench_regFile.vhd
-- Project Name:  regFile
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: regFile
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY testbench_regFile_vhd IS
END testbench_regFile_vhd;

ARCHITECTURE behavior OF testbench_regFile_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT regFile
	PORT(
		a1 : IN std_logic_vector(2 downto 0);
		a2 : IN std_logic_vector(2 downto 0);
		a3 : IN std_logic_vector(2 downto 0);
		w : IN std_logic_vector(7 downto 0);
		is_rw : IN std_logic;
		clk : IN std_logic;          
		r1 : OUT std_logic_vector(7 downto 0);
		r2 : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL is_rw :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL a1 :  std_logic_vector(2 downto 0) := (others=>'0');
	SIGNAL a2 :  std_logic_vector(2 downto 0) := (others=>'0');
	SIGNAL a3 :  std_logic_vector(2 downto 0) := (others=>'0');
	SIGNAL w :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL r1 :  std_logic_vector(7 downto 0);
	SIGNAL r2 :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: regFile PORT MAP(
		a1 => a1,
		a2 => a2,
		a3 => a3,
		w => w,
		is_rw => is_rw,
		r1 => r1,
		r2 => r2,
		clk => clk
	);

	clk_tb: PROCESS
	BEGIN
	wait for 50 ns;
	clk <= '1';
	wait for 50 ns;
	clk <= '0';
	END PROCESS;

	tb : PROCESS
	BEGIN
		wait for 100 ns;
		a3 <= "001";
		w <= "11111111";
		is_rw <= '0'; -- Escritura
		wait for 100 ns;
		a1 <= "001";
		a2 <= "010";
		is_rw <= '1'; -- Lectura
		wait for 100 ns;
		a3 <= "010";
		w <= "00111111";
		is_rw <= '0'; -- Escritura
		wait for 100 ns;
		a1 <= "001";
		a2 <= "010";
		is_rw <= '1'; -- Lectura
		wait; -- will wait forever
	END PROCESS;

END;
